This invention relates to computer systems. More specifically, this invention relates to the assignment of interrupts to expansion cards on a computer.
The Peripheral Component Interconnect (PCI) bus is an industry standard system bus for connecting peripheral devices to the host processor bus. FIG. 1 shows an exemplary computer system 100 incorporating a conventional PCI bus. Computer system 100 includes a central processing unit (CPU) 102 connected through a host/PCI bridge 104 to main memory 106 and upstream PCI bus 108. Typically, the motherboard for computer system 100 is provided with a set of electrical card edge connector sockets, or xe2x80x9cslots,xe2x80x9d each slot being adapted to receive a PCI card. Each PCI card, in turn, comprises at least one PCI device having a plurality of registers containing unique criteria such as Vendor ID, Device ID, Revision ID, Class Code Header Type, etc. The number of PCI cards that may be connected to a single PCI bus is limited, however, the PCI specification circumvents this limitation by allowing more than one PCI bus to exist in computer system 100.
FIG. 1 shows PCI bus 108 connected to PCI devices 110a-110c and to PCI-to-PCI bridge 114. PCI-TO-PCI bridge 114 provides a connection path between two independent buses, upstream PCI bus 108 and downstream PCI bus 116, and forwards all types of memory, I/O, and configuration commands between the interface to upstream PCI bus 108 and the interface to downstream PCI bus 116. Downstream bus 116, in turn, connects to PCI devices 110d-110g. Commonly used PCI devices include video cards, SCSI host adapters, and high-speed networking cards. PCI-TO-PCI bridge 114 may reside on a PCI interface card 116 having its own PCI bus 116 including PCI devices 110d-110g integrated on the card 116. Alternatively, PCI devices 110d-110g may be inserted into PCI bus connector slots provided on the downstream PCI bus 116. Each PCI device 110a-110f may contain one or more separate PCI functions (i.e., logical devices). A PCI device which contains only one function is referred to as a single-function device.
A more complete description of the PCI architecture can be found in xe2x80x9cPCI System Architecture,xe2x80x9d Fourth Edition, MindShare, Inc., and xe2x80x9cPCI/PCI Bridge Specification,xe2x80x9d revision 1.0, incorporated herein by reference.
At initial power-up, computer system 100 performs a Power On Self Test (POST) routine in which the configuration software in the computer scans the various buses in the system to determine what devices exist on the system and what configuration requirements they have. Each PCI device""s configuration registers must be initialized at startup time to configure the device to respond to memory and I/O address ranges assigned to it by the configuration software. During the POST routine, the BIOS discovers each PCI device and the device""s personal information, such as interrupt request number (IRQ#), bus master priority, latency time, and the like, are stored in the system is non-volatile random access memory (NVRAM). In addition, peripheral devices such as hard disks, CD-ROM readers, network interface cards, and video graphics controllers may be supplied by various hardware vendors. These hardware vendors must supply software drivers for their respective peripheral devices.
Various PCI interface control signals are used to control a PCI transfer. The Initialization Device Select (IDSEL) is an input to a PCI device and is used as a chip select during an access to one of the device""s configuration registers. Normally for a device on a PCI bus, one of the upper AD lines in the range AD[31:16] are connected to the device""s IDSEL pin. The PCI specification dictates which AD line is to be used for each available slot on a PCI bus, which ensures that no two devices on a particular bus are assigned to the same AD pin. Thus, in conventional computer systems, the IDSEL pin on each PCI device is hardwired to a pre-selected one of the sixteen available AD lines on the PCI bus.
FIG. 2 is a block diagram showing the connections of PCI devices 204-208 to PCI bus 200. AD lines 202 carry address and data information between PCI bus 200 and PCI devices 204-208. In the system shown in FIG. 2, address line AD16210 is connected to the IDSEL input on PCI device 204, address line AD17211 is connected to the IDSEL line of device 205, address line AD18212 is connected to the IDSEL line of device 206, address line AD19213 is connected to the IDSEL line of device 207, and address line AD20214 is connected to the IDSEL line of device 208. Resistive coupling may be used to connect the address lines to the IDSEL lines.
The system BIOS maintains information regarding the hardwired routings of the AD lines to the IDSEL line of each of the target devices, as outlined by the PCI specification, and this routing information is used by the BIOS to determine the device number for each device on the bus. For example, because device 204 has its IDSEL pin connected to AD 16, device 204 acquires the system numbering of xe2x80x9cdevice 0xe2x80x9d on that bus. Accordingly, device 205 having its IDSEL connected to AD17 becomes xe2x80x9cdevice 1xe2x80x9d on that bus. This numbering system continues through AD31 (not shown in FIG. 2), which would be connected to the IDSEL of device 15. Because the AD lines are hardwired to the pins which mate with the devices"" IDSEL lines, each device""s device number is determined by its location on the bus and can normally only be changed by modifying that device""s physical position on the bus, i.e., changing the slot into which the PCI card is inserted. Because embedded devices are not movable, the hardwired AD line connections cannot be modified.
Four PCI interrupt request lines (INTA#, FNTB#, INTC#, or INTD#) are available for PCI devices to generate interrupt requests in order to request servicing by the host processor. These four INT# lines are shares all of the PCI devices on the computer system. A multi-function PCI device, which takes the form of a physical package embodying between two and eight PCI functions, may implement up to all four of these interrupt pins. Each function within the package is permitted to use exactly one of these interrupt pins to generate requests, and that function""s Interrupt Pin register is used to indicate which of the package""s interrupt INT# pins is bonded to the function""s internal INTA# pin.
As described above, the Device ID number for each PCI device is determined by the AD line number connected to that device""s IDSEL pin. The Device ID, in turn, determines which of the input INT# lines on the bus is connected to the interrupt INTA# pin on the device. For devices on the motherboard, this INT# line assignment is flexible and can be determined by a mapping provided to the system BIOS. In a card which implements a PCI-to-PCI bridge and a secondary PCI bus (i.e., a bus that exists downstream of bus 0), the bridge specification dictates that the interrupt pins on the secondary bus""s PCI functions must be connected to the add-in card""s connector interrupt pins as indicated in Table I below.
As can be seen from Table I, the INTA# pin on device 0 is connected to the INTA# line on the bridge""s card. However, the INTA# pin on device 1 is connected with the INTB# line the bridge""s card, the INTA# pin on device 2 is connected with the INTC# line the bridge""s card, and the INTA# pin on device 3 is connected with the INTD# line the bridge""s card. Each device uses its INTA# pin to send interrupts to the host processor, while the processor uses different INT# lines to communicate with the INTA# pins on the individual devices on the bus. In a computer system having only four devices located on a bus, this staggered connection arrangement advantageously results in an efficient sharing of the four available interrupt INT# lines by providing each device with its own unique interrupt INT# line.
If a fifth device (device 4 in Table I above) is added to the bus, then that device""s INTA# pin is connected to the INTA# pin the bridge""s card. Because there are only four available interrupt lines, this arrangement forces device 0 and device 4 to share the INTA# interrupt line. Although the PCI specification was designed to anticipate this interrupt sharing, problems often arise. In some cases, the device driver may be poorly written or not fully PCI-compliant, which could result in poor sharing of interrupts and other compatibility problems. Even if the interrupt sharing is successful, because the interrupt handler must search through all the devices assigned to that interrupt in order to determine the proper device, many I/O cycles are wasted, causing performance to suffer. Accordingly, there is a need for an improved method of assigning shared interrupts to PCI devices.
In accordance with the present invention, a method for assigning PCI device interrupts performed by a computer system having a PCI bus comprises selecting a first assigned address line from a first plurality of address lines, said first plurality of address lines being connected through a multiplexer to a first IDSEL input on a first PCI device on said PCI bus, and controlling said multiplexer to channel a signal from said first assigned address line to said first IDSEL input on said first PCI device.
In accordance with another aspect of the present invention, the method further comprises selecting a second assigned address line from a second plurality of address lines, said second plurality of address lines being connected through a second multiplexer to a second IDSEL input on a second PCI device on said PCI bus, and controlling said multiplexer to channel a signal from said second assigned address line to said second IDSEL input on said second PCI device.
In accordance with yet another aspect of the present invention, a computer system comprises a PCI bus, a plurality of interrupt lines on said PCI bus, a first plurality of address lines on said PCI bus, a first multiplexer connected to a second plurality of address lines, said second plurality of address lines being a subset of said first plurality of address lines, a first PCI device on said PCI bus having a first IDSEL pin connected to said first multiplexer, and a first control line to said first multiplexer, said first control line providing a control signal to said first multiplexer to channel a first assigned address line in said second plurality of address lines to said first IDSEL pin.